LVD2EN=0, BUSMEN=0, LVD1EN=0, WDTEN=0, NMIEN=0, IWDTEN=0, SPEEN=0, RECCEN=0, VBATTEN=0, BUSSEN=0, OSTEN=0, RPEEN=0
Non-Maskable Interrupt Enable Register
| IWDTEN | IWDT Underflow/Refresh Error Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| WDTEN | WDT Underflow/Refresh Error Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| LVD1EN | Voltage-Monitoring 1 Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| LVD2EN | Voltage-Monitoring 2 Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| VBATTEN | VBATT monitor Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| Reserved | This bit is read as 0. The write value should be 0. |
| OSTEN | Oscillation Stop Detection Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| NMIEN | NMI Pin Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| RPEEN | RAM Parity Error Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| RECCEN | RAM ECC Error Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| BUSSEN | MPU Bus Slave Error Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| BUSMEN | MPU Bus Master Error Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| SPEEN | CPU Stack pointer monitor Interrupt Enable 0 (0): Disabled 1 (1): Enabled. |
| Reserved | These bits are read as 000. The write value should be 000. |